Chapter 1: Impedance

1.1  General Concepts
1.2  Discrete Electrical Components
1.3  Capacitors
1.4  Resistors
1.5  Inductors
1.6  Wires or Printed Circuit Board (PCB) Conductors
1.7  Impedance Between Two Ground Planes Within a PCB
1.8  Electrical Vias
1.9  Crystals


Chapter 2: Impedances of Selected Printed Circuit Board Components

2.1  Introduction
2.2  Non-Ideal Behavior Of Capacitors
2.3  Surface-Mount Capacitors
2.4  Through-Hole Capacitors
2.5  Capacitive Behavior Between The Top And Bottom Layers Of PCBs
2.6  Non-Ideal Behavior of Electrical Vias
2.7  Impedance Behavior of Crystals
2.8  Impedance Behavior of Light Emitting Diodes
2.9  Impedance Behavior of Ceramic Resistor Networks
2.10  Impedance Behavior of Chip Resistors
2.11  Printed Circuit Board Traces


Chapter 3: Ferrite EMI Filters

3.1  Introduction
3.2  Impedance Response of Multi-Layer Chip EMI Filters
3.3  Impedance Response of a Common-Mode Toroidal EMI Filter
3.4  Planar Magnetic Common-Mode EMI Filters
3.5  Designing Common-Mode Ferrite EMI Filters
3.6  Impact of Geometry On Impedance From Two Cylindrical Common-Mode Ferrite EMI
Filters


Chapter 4: EMI Counter-Measures For On-Board Integrated Circuits

4.1  Introduction
4.2  Mitigating The EMI From Integrated Circuits
4.3  Faraday Cages
4.4  Ferrite Disks


Chapter 5: Signal Integrity

5.1  Ringing Effects
5.2  Low-Pass Filtering
5.3  Reflections From Unmatched Transmission Lines
5.4 Crosstalk Between Adjacent 50ohm Striplines And Its Associated Radiated  
Emissions
5.5 Crosstalk Between Orthogonal 50ohm Striplines
5.6 Far-Field Electric Field And Near-Field Magnetic Field Radiation From Differential-
Mode Currents
5.7  Far-Field Electric Field And Near-Field Magnetic Field Radiation From Common-
Mode Currents
5.8  EMC Measurements Of The Impact Of Wire Gauge On Differential-Mode Radiated
Emissions
5.9  Device Ground-bounce, Power-bounce And Their Radiated Emissions
5.10  Electric And Magnetic Near-Field Radiated Emissions From Different Microstripline
Dielectric Thicknesses
5.11  Current Flow Through An Electrical Via


Chapter 6: Printed Circuit Board EMI Counter-Measures

6.1  Introduction
6.2  Minimize The Loop Areas For All Power and Power Return Paths
6.3  Minimize The Signal And Signal Return Loop Areas
6.4  Surround The Outgoing High-Speed Clock Traces With Additional Traces That
Comprise The Return Path Along With The Ground Plane
6.5  Avoid Routing Signal Traces Over Ground or Power Plane Cutouts
6.6  Utilize Buried Capacitance For Very High-Speed (>2-GHz) Applications
6.7 Scramble High-Speed Data Signals
6.8  Whenever Possible, Utilize “Twisting” Techniques On A PCB To Minimize Loop
Areas For Circuits In Which The Outgoing And Return Conductors Carry Equal And
Opposite Currents
6.9  Electrically Connect Multiple Ground Planes To Each Other Around
The Periphery Of The Board Through The Use Of Periodically Spaced Electrical Vias
6.10  Use Spread Spectrum Techniques, Such As Baseband Direct Sequence
Techniques, To Disperse The Energy From Bothersome Signals Over A Large
Frequency Range
6.11  Partition Mixed Analog/Digital PCBs Such That The Digital Portion Is Furthest From
The Cabling End Of The PCB
6.12  Filter The Rising/Falling Edges Of Output Clock Signals With Low-Pass Filters
Having 3-dB Frequencies Of About 1/(2tr)
6.12  Use The Stripline Topology Instead Of The Microstrip Topology For
Implementing PCB Transmission Lines
6.13  Keep All Connectors And I/O Connections On One Side Of The Board
6.14  Try Not To Route Any Signals On The Outer Layers Of The PCB
6.15  Use Properly Packaged Ceramic Capacitors For Bypass Functions
6.16  Use Appropriate Decoupling Capacitance Values Relative To The Capacitance
Between The Power And Ground Planes
6.17  Avoid Ground Plane Cutouts, Intended For Connector Pin Placement, That Affect
Signal Return Paths By Increasing Loop Areas
6.18  Avoid Running High-Speed Signals On The Outer Edges Of The PCB
6.19  Avoid Routing Clock Signals And High-Speed Signals Next To Power
Planes; Instead, Route these Signals As Close As Possible To Ground Planes
6.20  Minimize The Number Of Transmission Line Discontinuities
6.21  Try Not To Overlap Different Valued Power Planes
6.22  Whenever Possible, Avoid Jumping Signal Traces, Using Vias, Across Different
Reference Planes
6.23  Use Lowest-Profile IC Packages (e.g., TSOP, TSSOP, TQFP, and BGA), Instead Of
SOP, SSOP, or QFP Packages
6.24  Components Requiring Power And Ground Should Be Connected To The
Nearest Power And Ground Planes
6.25  Avoid Exciting Resonances Between Reference Planes
6.26  Select Integrated Circuit Chips That Have Multiple Power And Ground Pins
6.27  When Placing Several Differential Transmission Lines Side-By-Side, Place A
Reference Trace Between Adjacent Transmission Lines
6.28  Whenever Possible, Use Isolation Transformers To Reject Common-Mode Noise
Voltages On Balanced Conductors
6.29  Try To Use Transformers To Convert Single-Ended Signals Into Balanced
Differential Signals


Chapter 7: Printed Circuit Board Transmission Lines

7.1  Introduction
7.2  Microstrip Transmission Lines
7.3  Differential Microstrip Transmission Lines
7.4  Stripline Transmission Lines
7.5  Differential Stripline Transmission Lines
7.6  Embedded Coplanar Strips Without Reference Planes
7.7  Surface Coplanar Strips Without Reference Planes
7.8  Broadside Parallel Traces Without Reference Planes
7.9  Finding All Values Of h and W For A Specified Characteristic Impedance
7.10  EMC Ratings of Transmission Line Structures


Chapter 8: Radiation Through Cabinet Apertures

8.1  Introduction
8.2  Electric Field Shielding
8.3  The Slit or Slot Aperture
8.4  The Square Aperture
8.5  The Circular Aperture
8.6  Radiation When The Wavelength Is Smaller Than The Aperture
8.7  Arrays of Slit and Square Apertures
8.8  Safety Requirements Regarding Aperture Dimensions
8.9  Apertures Located On The Sides Of Enclosures
8.10  An Array of Slit or Square Apertures
8.11  Near-Field Radiation Patterns
8.12  Far-Field Radiation Patterns
8.13  Does Size Matter?
8.14  Ground Plane Effects On The Radiation Patterns
8.15  Magnetic Field Shielding
8.16  Waveguides
8.17  Shielding Effectiveness From Arrays Of Apertures:  A Time-Domain Approach


Chapter 9: Impact of Capacitor Packaging On Reactance (Impedance)

9.1  Introduction
9.2  Reverse Packaged Capacitors
9.3  Reduction of ESL by Using 0612-Packaged Capacitors Instead of 1206-Packaged
Capacitors
9.4  Reduction of ESL by Using 0508-Packaged Capacitors Instead of 0805-Packaged
Capacitors
9.5  Reduction of ESL by Using 0306-Packaged Capacitors Instead of 0603-Packaged
Capacitors
9.6  Interdigitated Capacitors
9.7  Resonant Frequency Measurements
9.8  Conclusion


Chapter 10: The Printed Circuit Board De-Coupling Function, Buried Capacitance and A
New Decoupling Capacitor Module

10.1  Introduction
10.2  Characterizing Buried Capacitance
10.3  Buried Capacitance Within The Printed Circuit Board’s Decoupling Function
10.4  Improving The Performance Of The 0.01uF / 0.01uF Structure
10.5  Experimental Results Of Radiated Emissions From Decoupling Structures
10.6  Conclusions


Chapter 11: Power Distribution

11.1 Goals Of A Power Distribution System
11.2 Groundbounce And Powerbounce
11.3 Ground Plane DC Voltage Loss
11.4 Power Distribution From An On-Board DC Source To A Switching Load
11.5 Decoupling Capacitance And High-Speed Switching Noise
11.6 Power Distribution From An On-Board DC Source To A Switching Load On A
Daughter Card
11.7 Estimating The Number Of Connector Ground Pins Per Signal Pin
11.8 Power Distribution Between Two Different Circuit Boards
11.9 The Role Of Embedded Capacitance For Minimizing Switching Noise
11.10 Determining The Value Of The Decoupling Capacitance
11.11 Identical Versus Different Valued Decoupling Capacitors And Cross Resonances
11.12 Power Plane And Ground Plane Resonances Without Decoupling Capacitors
11.13 Power Plane And Ground Plane Resonances With Decoupling Capacitors
11.14 Power Distribution To A Motherboard
11.15 Power Distribution To Multiple Loads
11.16 System Hierarchical Grounding

Appendix

Laboratory Experiments

Lab 1:  Loop Areas and Radiated EMI
Lab 2:  Measuring The Impedances Of Surface-Mountable Capacitors
Lab 3:  Measuring The Impedances Of Surface-Mountable Ferrite-Based Filters
Lab 4:  Shielding Provided By An Enclosure
Lab 5:  EMI Mitigation By Interconnecting Multiple Ground Planes
Lab 6:  EMI Mitigation By Placement of Reference Traces
Lab 7:  The Bypass Function
Lab 8:  Minimizing Crosstalk By Using Reference Traces
Lab 9:  Buried Capacitance

The interactive software learning environment covers the following 25
topics:

(1) Scrambling Data Signals For Minimizing Radiated Emissions
(2)  Far-field Radiation Patterns From Arrays of Square Apertures
(3) Far-Field Differential Mode and Common-Mode Radiation Patterns From Conductors
(4) Magnetic Near Field Distributions From Differential Mode and Common-Mode Signal
Propagation
(5) Printed Circuit Board Radiation From Reference Plane Cutouts
(6) Radiated Emissions From Crosstalk
(7) Decoupling Capacitors
(8) Designing Ferrite Common-Mode Filters
(9)  Radiated Emissions From Unmatched Transmission Lines
(10) Risetimes And Their Impact On Radiated Emissions
(11) Designing Transmission Lines For EMC Compliance
(12) Printed Circuit Board Radiation Due To Signal Jumping Between Different
Reference Planes
(13) Simulation Of An Actual Radiated Emissions Test
(14) Radiated Emissions From Transmission Lines With A Series Via Discontinuity And
A High Impedance Load


The purchaser will receive the above software interactive modules as well as all future
interactive modules as they become available through the author's research.

Designing For EMC Compliance With
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Disclaimer
The technical information contained within this website is for educational
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